Forum Discussion
Occasional ContributorfPLL Arria10 powerdown does nothing
Hi,
Thanks for your update. Regarding your latest observation on the PLL powerdown, as I check with the registermap, there seems to be no issue with the registers that you are accessing.
Just to check with you on the following:
1. Just wonder if the "Enable capability registers" and "Enable control and status registers" under the Optional Reconfiguration Logic tab are checked in the fPLL IP core during instantiation?
2. If after performing #1, similar problem persists. Would you mind to help performing a Modelsim simulation to check on the functional behavior to see if the observation is consistent?
Please let me know if there is any concern. Thank you.
Occasional Contributor- IMura
No, still doesn't work (I added the line assignment, regenerated the fpll).
- IMura
I guess I am just talking to myself on this intel forum. Hmm.
So I modified the generated vhdl file and set the enable_analog_resets => 1, now using signal tap, i can see that the locked signal behaves as expected when I put the fpll on powerdown. However I still have the problem
1. The clock to the refpin is active when the fpga is being configured : fpll locks after powerup, if I turn off the clock, it unlocks but if I turn the clock back on again, it locks again. So completely expected behaviour.
2. The clock to the refpin is inactive when the fpga is being configured : fpll NEVER locks after powerup.
Please, can somebody help me with this fpll behaviour ? Thank you.
