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arik's avatar
arik
Icon for New Contributor rankNew Contributor
1 month ago

FPGA programming before XCVR's ref clock is ready

Hi, I use F-Tile Agilex 7 and Q24.2. On power cycle (P.C) my reference transceivers clock is not ready and stable, so I do the following reset sequence to the System PLL (created for no stable XCVR...
Transceiver
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
18 days ago

Dear Customer,

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Altera Technical Support