Forum Discussion
arik
New Contributor
New ContributorFPGA programming before XCVR's ref clock is ready
Hi, I use F-Tile Agilex 7 and Q24.2. On power cycle (P.C) my reference transceivers clock is not ready and stable, so I do the following reset sequence to the System PLL (created for no stable XCVR...
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
The F-tile user guide provides the right guidance on the topic. Refer: https://docs.altera.com/r/docs/683872/26.1/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/guidelines-for-fgt-reference-clock
Key things to look for are:
1) F-tile system PLL IP settings for "Refclk #i is active at and after device configuration"
2) The reset assertion and de-assertion.
3) Ensuring that the input reference clock is really stable before you assert the signal en_refclk_fgt_i.
Please go through the guidance thoroughly and make sure it has been followed.
Regards
