FP_FUNCTIONS IP Pipelined?

Trying to use the Multiply and Addition functions out of the FP_FUNCTIONS IP. It is clear what the latency through the IP is for a given operation. However, it isn't clear if the operations are pipelined such that I can feed inputs in on every clock cycle and expect outputs on every clock cycle the latency number of cycles later. Anyone have any experience here that could help me understand expected operation?