For those who care about hardware resources with the Altera FFT IP core

We contacted the Altera support a while ago to indicate this potential improvement, but the person who answered did not show any interest.

When you say bit true performance, you mean the error compared to a "true" FFT ?

In the design implemented, the error on the FFT output was slightly higher if the same number of bits was used in output (16 bits here, obtained by truncating the output). But without truncating the output (which has 34 bits, because the FFT output that is 16 bits is multiplied by an complex exponential that is also 16 bits, and there are adders), the error on the FFT output was slightly lower. You can see this in Figure 9 of the pdf article (http://infoscience.epfl.ch/record/204540/files/implementing%20super-efficient%20ffts%20in%20altera%20fpgas.pdf).

Having 34 bits instead of 16 bits can be or not annoying, depending on the process after the FFT (for example if there is a detection just after, it will not be a problem). But this is the design we implemented, there are probably smarter ways to do it that could improve the accuracy.

Otherwise, I don't see any additional penalty with the proposed implementation. I did not try to evaluate the maximum running frequency, but I don't think it would decrease since only simple elements are added, as you can see in the actual implementation shown in Figure 8 of the pdf article.

Jérôme