For those who care about hardware resources with the Altera FFT IP core

Dear all,

Apparently, there are quite a few users of the Altera FFT IP core on this forum. The hardware resources used by the FFT can be very high (especially if the FFT length is high), so for those who really care about the amount of resources, it's possible to reduce the memory usage, at the expense of a more complicate design (and possibly a small increase of the logic and DSP blocks, it depends on the FFT options considered).

The details can be found here : http://www.eetimes.com/author.asp?section_id=36&doc_id=1325667, where a pdf explaining all this in details and a zip file with example projects are available.

In summary, by applying the principle of the radix-2 FFT (separating a signal in even and odd samples) and using an Altera FFT of size N/2 instead of N, it is possible to reduce the memory by about 30/40 % keeping the same processing time. This is a bit strange, but it works; a real design has been done to verify this.

For the designer that wants to use this, it complicates the things because the proposed design requires additional adders, a multiplier, a complex exponential generator (this can be done with an NCO or a pre-initialized memory ), a "small" memory, and blocks that perform scaling. But if in some cases it can save dozens or hundreds of memory blocks, it can worth it.

I hope this can help some of you.

Jérôme