Floating point accumulator - feedback loops

Hello,

I am attempting to design a single precision floating point accumulator. DSPB reports that a latency of at least 9 clocks is needed in the accumulation loop to allow for the floating point addition logic. As a consequence the accumulator can only run at 1/9 x the clock rate. My design needs it to run at the full system clock rate.

I can think of several ways of solving this, e.g. by instantiating 9 accumulators (by vectoring the input signals) and running each at 1/9 the clock rate. In an RTL design I would use a counter to sequence the data to the accumulators.

However I am fairly new to DSPB and wondered if the tool will allow a smarter way of achieving this. My first thoughts were to use some from of decimation block on the data that feeds the accumulators, but I am trying to stick with the Advanced block set, which does not have these.

Any help will be greatly appreciated.

Thanks,

Terry.