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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
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Fitter was unable to place an EMIF with a differential clock

I can see from this thread that a differential (LVDS) EMIF PLL reference clock is only supported in LVDS I/O banks (and not 3 V I/O banks) in Arria 10: https://community.intel.com/t5/Programmable-De...
  • hcom's avatar
    hcom
    4 years ago

    @AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.

    Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.

KCMurphy's avatar
KCMurphy
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

There are some constraints that are not immediately apparent from the reference material. One thing is that the DQS pins may only go on certain pins, and that the data pins associated with that DQS pin must be in the same "pin-group" as the DQS. This is due to the hard controller having fixed assignments. The Pin Planner's "DQS" legend is badly wrong and most of the documentation is confusing at best.

In Pin Planner, go to View/Show/Show DQ-DQS pins/your mode (x4, x8, etc). Note the color blocks. Similarly for the command pins, which are also forced, at least if you are using the hard controller. This allowed me to get LPDDR3 to fit.