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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Fitter was unable to place an EMIF with a differential clock

I can see from this thread that a differential (LVDS) EMIF PLL reference clock is only supported in LVDS I/O banks (and not 3 V I/O banks) in Arria 10: https://community.intel.com/t5/Programmable-De...
  • hcom's avatar
    hcom
    4 years ago

    @AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.

    Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.