Forum Discussion
Occasional ContributorFitter was unable to place an EMIF with a differential clock
@AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.
Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.
Regular ContributorThe example design is a design that has been generated by the Quartus software.
The design contains the components that are needed for the IP in order to work.
The point that I showed you in the example design is by changing the FPGA I/O termination, you should be able to use 3V I/O bank.
The A10 EMIF handbook has stated this configuration.
In your design, the top level file needs to edit because one signal has been disable from the EMIF IP.
It's oct signal. By disabling oct signal in your top level file, your design can be compiled.
I will attached the your design later.
Regards,
Adzim
- AdzimZM_Altera
The attachment is your design.
I have disable the oct signal in your top level file.
hcom@AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.
Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.
