Forum Discussion
hcom
Occasional Contributor
Occasional ContributorFitter was unable to place an EMIF with a differential clock
I can see from this thread that a differential (LVDS) EMIF PLL reference clock is only supported in LVDS I/O banks (and not 3 V I/O banks) in Arria 10: https://community.intel.com/t5/Programmable-De...
@AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.
Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.
AdzimZM_Altera
Regular Contributor
Regular Contributor
hcomOccasional Contributor
Occasional Contributor@AdzimZM_Intel This doesn't seem to change anything. Termination works fine with a single-ended PLL reference clock... and the fitter still fails with an LVDS reference clock, even if I disable termination.
Therefore, the problem does not seem to be related to this termination.
I sent you my project in a previous post, so you could have checked this.
