Forum Discussion
Occasional ContributorFitter was unable to place an EMIF with a differential clock
@AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.
Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.
Regular ContributorHi Harry,
When you want to use the 3V I/O bank, you need to disable the calibrated OCT for A/C signals, CLK signals and DQ signals.
After you changed the setting in the EMIF IP, make sure that you regenerate the IP.
Regards,
Adzim
hcom@AdzimZM_Intel How do I do that? The only option I can see related to on-chip termination in the EMIF IP is in FPGA I/O -> PHY Inputs:
Choosing either "LVDS with On-Chip Termination" or "LVDS without On-Chip Termination" seems to make no difference at all. The build still fails with the same errors.
I sent you my project in a previous post, so you can confirm this yourself if you want.
