Forum Discussion
hcom
Occasional Contributor
Occasional ContributorFitter was unable to place an EMIF with a differential clock
I can see from this thread that a differential (LVDS) EMIF PLL reference clock is only supported in LVDS I/O banks (and not 3 V I/O banks) in Arria 10: https://community.intel.com/t5/Programmable-De...
@AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.
Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Herry,
Your DQ and DQS signals should required the termination right.
If you make the termination assignment for the DQS or DQ signals, the Quartus will show the error like below.
The 3V I/O bank does not support the internal Vref generation which I think that the DQ for DDR3 required the Vref.
Maybe Bank 2L is not suitable for the DQ signal and you should use other I/O bank for this signal.
Thanks,
Adzim
