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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Fitter was unable to place an EMIF with a differential clock

I can see from this thread that a differential (LVDS) EMIF PLL reference clock is only supported in LVDS I/O banks (and not 3 V I/O banks) in Arria 10: https://community.intel.com/t5/Programmable-De...
  • hcom's avatar
    hcom
    4 years ago

    @AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.

    Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello Herry,


I think the I/O Bank 2L which is the 3V I/O bank is not supports the termination.

You can refer to section 5.1 on page 100 of " Intel Arria 10 Core Fabric and General Purpose I/Os Handbook".

I think that is the main reason on why you cannot make the DQ pin placement in the Bank 2L.


Regards,

Adzim


hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

@AdzimZM_Intel I'm not sure which part of that section you are referring to exactly. Are you referring to the part that says that single-ended I/O in 3 V I/O banks don't support "RD on-chip termination (OCT)"?

How do I know which single-ended I/O in my design needs "OCT"?