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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
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Fitter was unable to place an EMIF with a differential clock

I can see from this thread that a differential (LVDS) EMIF PLL reference clock is only supported in LVDS I/O banks (and not 3 V I/O banks) in Arria 10: https://community.intel.com/t5/Programmable-De...
  • hcom's avatar
    hcom
    4 years ago

    @AdzimZM_Intel My understanding from the documentation is that disabling all the on-chip termination damages performance.

    Since it is so difficult to get clear and reliable information from Intel (and so much time has already been wasted in this pursuit), we decided to redesign our hardware to use a single-ended reference clock.

hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

@AdzimZM_Intel I am trying to use Bank 2L and Bank 2K. As far as I understand, they are "adjacent" because they are next to each other in this diagram:

I have attached a minimal project (Quartus 21.3 Pro), containing only the EMIF. This reproduces the error:

There is only 1 pin assignment. If I remove this, then the project builds without error:

hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

@AdzimZM_Intel Have you looked at the project I attached for you? Can you offer any advice?