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ArleySalvador's avatar
ArleySalvador
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Fitter can not place PERST pin for Multichannel DMA PCIE

Hi guys, I am trying to compile the Example Design for Multichannel DMA PCIe IPCore. However the fitter plan stage failed and the following error has been reported. The issue appeared when I...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi Arley,

    We do not receive any response from you to the previous answer that I provided.

    Also, I strongly believe that my previous answer had solve your problem (Please correct me if I am wrong)


    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel


Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Arley,


Can you try to


set_instance_assignment -name VIRTUAL_PIN ON -to *pipe_sim_only*

set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to pcie_rstn_pin_perst

ensure pcie_rstn_pin_perst is whatever this port is called in your top level.


the information contained within the S10 PCIe Example Design User Guide,

can you ensure that you have the following two assignments in your test project:


Regards

Wincent_Intel


  • ArleySalvador's avatar
    ArleySalvador
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Wincent,

    I just confirmed that both constraints are present in my QSF.

    Additionally, the pcie_rstn_pin_perst pin is connected to the top level interface.

    I have attached the QAR file here.

    Regards,

    Arley