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Fuad1's avatar
Fuad1
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3 years ago

FIR II ip simulation warning

I’m using Intel Quartus prime lite edition and I’m getting the following frequent/multiple warnings when simulating the FIR II IP using Questa Intel starter FPGA edition: Warning: NUMERIC_STD.TO_SI...
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Please share your project, I will have a look once and try to resolve. Please share the below details as well.


1) Which Operating system you are using?

2) Which Quartus Software version you are using?

3) Which device(OPN) you are targeting?

4)Which FPGA Development Tool you are using?


Thank you

Kshitij Goel


  • Fuad1's avatar
    Fuad1
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi K**bleep**ij,

    Herewith the relevant project files. Open the project DUC and then RTL simulation and the simulation will run automatically then you will see the following multiple warnings printed in Questa:

    # ** Warning: NUMERIC_STD.TO_SIGNED: vector truncated

    # Time: 5228800 ns Iteration: 1 Instance: /tb/DUT/FIR_I/DUC_FIR_ast_inst/real_passthrough/hpfircore_core

    # ** Warning: NUMERIC_STD.TO_SIGNED: vector truncated

    # Time: 5230080 ns Iteration: 1 Instance: /tb/DUT/FIR_Q/DUC_FIR_ast_inst/real_passthrough/hpfircore_core

    I’m using Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition and the operating system is windows 11. Kindly advise.

    Regards,

    Fuad