Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHye Alex,
I assume you're using the FIR Compiler II ? If so: Under the tab 'implementation options', there is a box 'Frequency Specification'. If the Clock frequency and input sample rate are not equal, the FIR II compiler will use the relation between these two to optimize the hardware, and you'll have the EOP and SOP signals. If you'll make them equal (so i've tried with your settings) you'll end up with 16 bits input and full-scale output when you chose not to truncate/round. I'm using quartus v10.1sp1, so maybe there is a difference.. Grtz, Olaf