FIR filter design with IEEE 754 half-precision floating point

Per FvM's comment:

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As an additional comment, all required rounding/truncation/saturation operation are handled in the IEEE fixed point package.

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There's an example zip file (vhdl_fixed_pkg_example.zip) in this thread:

http://www.alteraforum.com/forum/showthread.php?t=37555&page=6

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A convenient way to implement FIR filters that take advantage of the FPGA hardware is to use the Altera FIR compiler.

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This is also a good point. The FIR filter example in the zip example I created to match the example delivered with the BeMicro-SDK, but with more flexibility. Altera's FIR tool will generate a more optimal FIR given that 'optimal' depends on the technology. The slides linked above have more comments (and images) on this.

Cheers,

Dave