Altera_Forum
Honored Contributor
16 years agoFIR filter design in VHDL
Hi All,
I am new to DSP/FIR filter design. I have a few basic questions in regards to the FIR filter design in VHDL. I have to design 1.FIR High Pass Filter at 300 Hz (basically to remove 30 Hz and to pass 1020 Hz). 2.FIR Low Pass Filter at 100 Hz (to pass 30 Hz). My Cyclone 3 FPGA currently occupies 75 % of resources and have only 10 multipliers left. Because of this , I decided to go with the Time Multiplexed architecture design. Hence I am storing the unfiltered input data into RAM and this goes to the MAC (Multiply and Accumulate ) unit which also gets a 16-bit coefficient data from the Coefficient ROM. Now I am planning to use the Altera Embedded BlockRAM memories to do this. But now the question is how am I going to know the depth of the RAM? which in turn means I need to calculate the number of taps required for both these filters. My input data is 16 bit wide and output is also 16-bit wide. Can someone give me ideas on this? Many thanks in advance BPR