Honored Contributor
Honored ContributorHi,
I don't mean that 1.0000 filter design tools produce coeffs normalised to a sum of 1. This guaratees a dc gain of 1 in a pc model (or in DSP), but in FPGA hardware they are scaled up to say 12 bits signed. It is this scaled sum that I am talking about. All coefficients will be rounded integers with the maximum occuping up to the roof. So add up the scaled coefficients and multiply their sum by maximum input value then it tells you how many bits you need...this decides MSB discarding. At the output you truncate off 11 LSB bits. This gives you back the unitary dc gain because you scale up then down equally.
