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Honored Contributor
Honored ContributorFIR and CIC MegaCores Altogether
Hi,
I have instantiated FIR II MegaCore as a Pulse-Shaping and upsampling by 8 filter, now I want to use CIC MegaCore after FIR to interpolate the signal... I didn't use Back Pressure feature in FIR. Simulation shows that signal is not interpolated... almost the same. In the generated test bench of the CIC IP, I noticed that input is allowed only when "in_ready" signal is high... when it's low the input is kept hold. I tried to do the same thing using Back Pressure feature in FIR IP, but because ModelSim doesn't allow mixed-HDL simulations (what a shame!) I couldn't verify. So, I used SignalTap instead... plotting the result on MATLAB shows a completely distorted signal! So... How do I use CIC along with FIR MegaCore? Can you please provide an example?15 Replies
Altera_Forum1) If you are going to mix at 10Mhz then you need to upsample(interpolate) to 10MHz.
2) 10000KHz/178.571KHz is a weird fraction and = 10000000/178571 that I doubt if it simplifies any further. Then you have to interpolate by num/8 (8 done in rrc) and decimate by denum. I don't know if your cic will support that sort of figure. 3) use system clock of 10MHz on both fir and cic with a fifo in between to control rate. You cannot run cic output at 10MHz unless you upsample to 10MHz through FIR+CIC Who decides 178.571KHz. Is't an audio application?- Altera_Forum--- Quote Start --- 1) If you are going to mix at 10Mhz then you need to upsample(interpolate) to 10MHz. --- Quote End --- I am going to mix at 100 MHz, 10 MHz is just an intermediate frequency, I think I am going to use a compensation filter with interpolation factor of 10. --- Quote Start --- 2) 10000KHz/178.571KHz is a weird fraction and = 10000000/178571 that I doubt if it simplifies any further. Then you have to interpolate by num/8 (8 done in rrc) and decimate by denum. I don't know if your cic will support that sort of figure. --- Quote End --- What I actually did is that I divided the 50 MHz by 280, I didn't write all of the resultant fraction but it exists in hardware. So I don't think I'll need fractional interpolation, or will I? --- Quote Start --- 3) use system clock of 10MHz on both fir and cic with a fifo in between to control rate. You cannot run cic output at 10MHz unless you upsample to 10MHz through FIR+CIC --- Quote End --- How do I upsample through FIR+CIC? I didn't get this. --- Quote Start --- Who decides 178.571KHz. Is't an audio application? --- Quote End --- I did :D I chose to send audio over air for demonstration purposes.
- Altera_Forum
I am a bit lost between figures. (10MHz,50MHz,280,100MHz).
if your symbol rate is 50000/280 then you don't need fractinalupsampler you need to go up from 50000/280 to 100000 = 560 8 in rrc, 10 in comp filter, 7 in cic well just use a fir interpolator at 70 or two firs at 10 and 7 or rrc to go up by 56, fir by 10 - Altera_Forum
Yes that's what I'm going to do.
But do you know why ModelSim simulation failed to give correct CIC output? It's the same design... nothing changed. - Altera_Forum
I figured it out... reset signal of the CIC was going high before any clock edge rises.
Do not you just love this view :D https://www.alteraforum.com/forum/attachment.php?attachmentid=10294
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