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VParu1's avatar
VParu1
Icon for New Contributor rankNew Contributor
6 years ago

files generated during ddr2 sdram controller with UNIFY instantiation does not have top simulation test bench and DDR2 model

Hi, I am bringing up communication between stratix iv fpga and ddr2 sdram. For that I have instantiated DDR2 SDRAM Controller with UNIFY using Quartus prime standard edition 16.0. I want to simula...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi, Now I understand the reason. Since you are using UniPHY, so the document that you referring is incorrect. the document that you are using now is ALTMEMPHY which is obsolete.

The IP that you instantiate in the QII 16.0 is UniPHY which include in this document:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf#page=406

For uniphy, after you generate the IP with example design, it will create a folder <variable>_example_design

You may refer to the uniphy documentation as above on how to use the design.