Forum Discussion
VParu1
New Contributor
New Contributorfiles generated during ddr2 sdram controller with UNIFY instantiation does not have top simulation test bench and DDR2 model
Hi, I am bringing up communication between stratix iv fpga and ddr2 sdram. For that I have instantiated DDR2 SDRAM Controller with UNIFY using Quartus prime standard edition 16.0. I want to simula...
BoonT_Intel
Frequent Contributor
Frequent ContributorAs what I remember, for this old device, after you click on the generation, it will pop-up a window to ask you either want to generate the example design, you have to tick the option to generate example design then click ok. It only will generate the testbench file for you.
VParu1New Contributor
New ContributorHi,
I was selectinge generate example design option, it only generates the example desing project but didn't generate the testbench or memory model.
