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Arley's avatar
Arley
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3 years ago

Fiiter can not place PERST pin for Multichannel DMA PCIE

Hi guys, I am trying to compile the Example Design for Multichannel DMA PCIe IPCore. However the placement stage failed and the following error has been reported. The issue appeared when I init...
Arley's avatar
Arley
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3 years ago

Hi Wincent,

1) Regarding to LVDS SERDES,

I have successfully synthesized the same project for 1SG065HH3F35E3VG device and back-annoted the voltage pattern, as you can see below.

set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to xcvr_tx_out*

set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to xcvr_rx_in*

Then I constrained the project for 1SG040HH3F35E3VG using the same IO Standard and I have gotten the same issue.

2) Regarding to IOPLL,

after yout last message I have tried to constraint only the pins xcvr_rx/tx, perst and refclk. I assume that the correct pin to conect refclk is PIN_AC28 according to the 1SG040_HF35 pin list provided by Intel (attached the QSF)

3) Regarding to PCIe Gen3x16 from lane 1-4, I am trying to use PCIe Gen3x8 with 1SG040HH3F35E3VG. I am not sure which configuration you have suggested to check.

Since it is successfully compiling for 1SG065 with no pinning constraint, shouldn't it compile for 1SG040 as well?

Regards,

Arley