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Arley's avatar
Arley
Icon for New Contributor rankNew Contributor
3 years ago

Fiiter can not place PERST pin for Multichannel DMA PCIE

Hi guys, I am trying to compile the Example Design for Multichannel DMA PCIe IPCore. However the placement stage failed and the following error has been reported. The issue appeared when I init...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


For Error 175006 :

You may see this error in the Intel® Quartus® Prime Pro software when using LVDS SERDES Intel FPGA IP with Intel Stratix® 10 devices.

This error occurs when the input clock signal of the IOPLL is being sourced through the FPGA core.

To avoid this error, provide the input clock signal to the IOPLL through dedicated clock pins.


Stratix 10 support PCIe Gen3x16 from lane 1-4 , can you please check the table below and ensure that the configuration is correct ?


Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago