FIFOed UART Qsys Generation Error with Qsys Standard v18.1

You mention that you was able to reproduce the issue, are you using windows 7? As mention, I am using windows 10 and redhat. Would you able to use windows 10?

For reset password problem, can you file a new thread to address this differently?

Today I tried again and I am getting error in windows 10, seems like I might have choose the wrong language in my previous test.

Error: fifoed_avalon_uart_0: Failed to generate module Test_fifoed_avalon_uart_131_rxorl4y

Info: fifoed_avalon_uart_0: Done RTL generation for module 'Test_fifoed_avalon_uart_131_rxorl4y'

Error: Generation stopped, 1 or more modules remaining

Info: Test: Done "Test" with 3 modules, 1 files

Error: qsys-generate failed with exit code 1: 2 Errors, 3 Warnings

If you swith from VHDL to verilog for simulation, the error goes away. Since modelsim able to support mixed language simulation, you will have to choose Verilog instead.

Please note that there will be no fixed/support for old version of IP (in your case Q13.1). We are sorry to inform that.

Unfortunately, nope. Usually, if the IP official support from the engineering, you will not need to downloading in the website. It will be exist in the Installed IP when you install the Quartus Prime.

However, if you wish to have this IP. What I can do is file an enhancement to our engineering to include this IP in the future release of Quartus Prime Pro.

So I understand that this IP never was really under support from Intel. I think that mainly customers in the low-cost field using the Quartus Prime Standard edition would benefit the most. I don't work with the Pro edition but I think that other users could benefit from it. But who knows, in a data center a UART is probably not the interface of choice.

understood, I will try to get this enhancement done on Standard as well.