Contributor[FIFO]
Hi,
I'm about the "Asynchronous clear" signal in the FIFO IP - what's its functionality? What does it actually clear?
Once this signal is asserted, does it bring both the read and write pointers to point to the same FIFO entry? Should this be the first entry ?
Thanks!
Hi Dmitry,
The FIFO Intel® FPGA IP core supports the synchronous clear (sclr) and asynchronous clear (aclr) signals, depending on the FIFO modes. The effects of these signals are varied for different FIFO configurations. The SCFIFO supports both synchronous and asynchronous clear signals while the DCFIFO support asynchronous clear signal and asynchronous clear signal that synchronized with the write and read clocks. You may take a look at below link for different scenario and details about async clear
