FFT Megacore sink_ready never goes to 1

Hello,

I am facing a similar problem with the FFT IP core, however, my issue is different in that sink_ready does not always remain 0, but becomes don't care (StX).

I have looked at similar posts, and some of those problem (including the one in this thread) seemed to have been because of the reset_n input. I assert (set to 0) this signal and keep it asserted for many clock cycles (about 100), and sink_ready is 0 during this time. One cycle after I de-assert reset_n (set to 1), sink_ready becomes X. I also tried making this de-assertion happen at both the falling and the rising edge of the clock, but neither way worked.

I am using variable streaming mode, with fixed-point data representation. I thought the problem could be that I set the input values before the core is ready, so I assigned don't cares to input real and imaginary parts to avoid this. I have also looked at the example design for this core generated by QSYS, and have not been able to find what I am doing wrong.

I would appreciate it if anyone could let me know if they have seen this problem before and/or know how to solve it.