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Altera_Forum
Honored Contributor
17 years agoHi,
I got good news, for the problem (sink_valid goes low half way during input) the mistake was I did not turn on Global Clock Enable during code generation. The pin "clk_ena" needs to be there and set high for it to work properly, other wise there will be a warning like this: Can't find signal in vector source file for input pin "l fft_test1 l fftblock: inst l asj_fft_sglstream_fft_81 : asj_fft_sglstream_fft_81_inst l clk_ena"