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Honored Contributor
Honored ContributorFFT 8.0, sink_ready de-asserted
Hi, I am trying to test the functionality of FFT version 8.0. The device family that I am using is Cyclone II. Below is the parameter of the FFT: Transform Length: 64 points Data Preci...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ok i made my own test bench and tested the core (8.0sp1). i still can't reproduce your error, everything looks fine. :mad: your state machine timing looks right to me. how are you feeding the real/imaginary data to the core? --- Quote End --- Hi, Thanks for the efforts thepancake. http://www.alteraforum.com/forum//images/icons/icon7.gif The real/imaginary data comes from a FSM code that I wrote in VHDL. The code was nothing confidential, I just create it to test the FFT. Here, please have a look at it. I use functional simulation mode to test it. We can all learn from it.
