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ok i made my own test bench and tested the core (8.0sp1). i still can't reproduce your error, everything looks fine. :mad:
your state machine timing looks right to me. how are you feeding the real/imaginary data to the core?
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Hi,
Thanks for the efforts thepancake.
http://www.alteraforum.com/forum//images/icons/icon7.gif The real/imaginary data comes from a FSM code that I wrote in VHDL. The code was nothing confidential, I just create it to test the FFT. Here, please have a look at it. I use functional simulation mode to test it. We can all learn from it.
Honored Contributor
