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Altera_Forum
Honored Contributor
Honored ContributorFatal: (vsim-4) when trying to use SDRAM Controller Generic Memory Model
I'm trying to simulate a Qsys system with a Nios II processor running code from an external SDRAM, with Modelsim ASE. In order to get a simple RTL simulation, I would like to use the Altera Generic M...
Altera_ForumHonored Contributor
Honored ContributorThe inizialization file was set correctly from the beginning, although I can't understand how.
Anyway, I have the feeling that Altera SDRAM functional model isn't good at all: the problem with Modelsim is that this VHDL istantiates a big mem_array (array of std_logic_vectors) as a signal instead of as a variable, so causing Modelsim to go out of memory (I read somewhere on the web that mem_array should be instantiated as a variable to avoid this problem). Again, can anyone from Altera give me any kind of suggestion? Regards, Lorenzo
