F-Tile PCIe Root port - rx_st_hdr_o

Hi Serge93 

The signals rx_st_hdr_o[127:0] are valid when rx_st_sop_o=1 and rx_st_valid_o=1, as these conditions indicate the start of a valid TLP packet on the RX Avalon-ST interface. 
However, this does not imply that rx_st_data_o[127:0] is also valid. The F-Tile RX interface uses separate parallel buses for header and data. The validity of rx_st_data_o[127:0] is determined by the TLP type, specifically the Fmt field in the TLP header carried on rx_st_hdr_o: 

• When Fmt[2:0] = 000 or 001, the TLP has no data payload (e.g., Memory Read, Completion without Data), and rx_st_data_o must be ignored. 

For a Memory Read (MRd) request, the TLP consists of a header only with no data payload.
Please let me know if this addresses your questions. 

Thanks. 
Best Regards, 
Ven