extract only even lines from interlacer

Thank you for your reply, nice idea!

so if i understood, i need to modify the packet nibble before entering the interlacer to have only one type of output lines (even in my case).

i need a custom component for doing that, for keeping the ready latency to 1, i need to insert a fifo too.

Maybe is more convenient to do my interlacer since i have to do the input and output streaming interface anyway