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Vamsi_21's avatar
Vamsi_21
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2 years ago

ethernet_100g_loopback_off

Hi, I have generated a low latency 100g design example by following the guide below: https://www.intel.com/content/www/us/en/docs/programmable/683371/16-1/quick-start-guide.html I tested the s...
Ethernet
Chris039's avatar
Chris039
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

You can probably try running some example design and compare the pin assignment between the working version and the one you are seeing this error.

Vamsi_21's avatar
Vamsi_21
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,
The compilation _test_design is the only working version for which i got same results for both loop_on and loop_off as i mentioned earlier.
For the hardware_test_design there is no working version , I had always got the error:

"TTK failed reading from PHY slave, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset."
  • Chris039's avatar
    Chris039
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I cannot find the hardware_test_design in the QAR that you have shared earlier. I tried to generate an example design using the ex_100g.ip. I notice that the pin assignment for the compilation_test_design in your QAR is different from the one generated.

    Can you share your latest compilation_test_design and hardware_test_design for comparison? Are you using this devkit?

    https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-gx.html

    I believe you have to use the hardware_test_design for the hardware test but somehow the pin setting or clock input has problem.