Forum Discussion
Vamsi_21
Occasional Contributor
Occasional Contributorethernet_100g_loopback_off
Hi, I have generated a low latency 100g design example by following the guide below: https://www.intel.com/content/www/us/en/docs/programmable/683371/16-1/quick-start-guide.html I tested the s...
Yi
New Contributor
New ContributorI might find why you failed in board test, after open the .qar file, I found that the design you are using is the compilation test design, under folder:
/eth_100g_a10_22_2_0_94_restored/compilation_test_design
The compilation design is only for compilation test, which is not set for the board test.
To try on board, you can use the design file in folder /hardware_test_design , this should be the ready design that works for target dev kit.
Let me know if this works for you, thanks.
Vamsi_21Occasional Contributor
Occasional ContributorHi,
I have tried to test on the dev kit with the design file in the /hardware_test_design but I am getting master_write _32error in the system console window.
Below I am attaching the screenshot the error.
