eSPI Agent Core, Virtual Wire PLT_RST#

Hello,

Feedback from Engineering, we have tested with MAX10 and Arria 10. Both can see the pltreset_n virtual wire at the output port.

MAX10 we tried on Quartus 18.1.

Arria 10 we tried on Quartus 22.3.

When generating the IP, you need to select virtual wire channel or all chanels like below:

below is the screen shot from virtual wire index table, taken from Embedded peripheral IP userguide, eSPI chapter. The direction is Host to Agent(output). The peripheral channel allows you to communicate between the eSPI host and the
eSPI endpoints located at the agent side (example: PORT80). To reset the channel, use the platform reset (PLTRST_n Virtual Wire).

After compilation, you will see the "pltrst_n" output port from eSPI LPC bridge IP.

Below is RTL viewer for Arria 10:

and below is RTL viewer for MAX10:

There is limitation you need to consider on the clock ratio :

regards,
Farabi