eSPI Agent Core, Virtual Wire PLT_RST#

Hi,

I think it is a FPGA issue.

My questions again:

We are using the Intel eSPI Agent Core in an Intel FPGA.

We need the eSPI virtual wire PLT_RST# as a main reset on our mainboard . The virtual wire PLT_RST# is used internally by the eSPI Agent core. Unfortunately this signal is not led out of the IP core as port.

1. Is there a recommended solution for getting out a reset output signal from the IP core?

2. Is it planned in a next version of eSPI Agent Core to lead the virtual wire PLT_RST# out of the core as a virtual wire port like the other virtual wires?

Regards

Wolfram