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WFitt's avatar
WFitt
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3 years ago

eSPI Agent Core, Virtual Wire PLT_RST#

Hi, We are about to use the Intel eSPI Agent Core in a FPGA on our mainboard for communication with an Intel Elkhart Lake CPU module. Actually we need the virtual wire PLT_RST# as a main reset o...
Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


I am sorry, we need more clarification on what problem do you have related to FPGA?

This forum is for supporting FPGA issues.


regards,

Farabi


  • WFitt's avatar
    WFitt
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi,

    I think it is a FPGA issue.

    My questions again:

    We are using the Intel eSPI Agent Core in an Intel FPGA.

    We need the eSPI virtual wire PLT_RST# as a main reset on our mainboard . The virtual wire PLT_RST# is used internally by the eSPI Agent core. Unfortunately this signal is not led out of the IP core as port.

    1. Is there a recommended solution for getting out a reset output signal from the IP core?

    2. Is it planned in a next version of eSPI Agent Core to lead the virtual wire PLT_RST# out of the core as a virtual wire port like the other virtual wires?

    Regards

    Wolfram