Forum Discussion
J314
New Contributor
New ContributorError(18694) with LVDS SERDES IP
The planned design is to be implemented on a Cyclone 10GX and compiled with Quartus Prime Pro 22.4. In the design an external clock at I/O bank 2L is provided. I want to communicate with LVDS signals...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
You may refer to this handbook, https://www.intel.com/content/www/us/en/docs/programmable/683775/current/guideline-lvds-reference-clock-source.html.
It mentioned that if the reference clock input comes from other I/O banks, this source must come from another I/O bank and not from other sources such as IOPLL IP.
Regards,
Aqid
