Forum Discussion
J314
New Contributor
New ContributorError(18694) with LVDS SERDES IP
The planned design is to be implemented on a Cyclone 10GX and compiled with Quartus Prime Pro 22.4. In the design an external clock at I/O bank 2L is provided. I want to communicate with LVDS signals...
FvM
Super Contributor
Super ContributorHello,
above quoted solutions 1 and 3 are apparently erroneous. Nothing related to error(18694) has been fixed in QPP 20.1.
As for a possible solution, see my comment in
https://community.intel.com/t5/FPGA-Intellectual-Property/SERDES-IP-not-compiling-after-migrating-to-Quartus-Pro-23-1/td-p/1448743
As long as no solution is provided by Intel, I'd use QPP18.0 (solution 4) for existing designs that can't implement solution 2.
above quoted solutions 1 and 3 are apparently erroneous. Nothing related to error(18694) has been fixed in QPP 20.1.
As for a possible solution, see my comment in
https://community.intel.com/t5/FPGA-Intellectual-Property/SERDES-IP-not-compiling-after-migrating-to-Quartus-Pro-23-1/td-p/1448743
As long as no solution is provided by Intel, I'd use QPP18.0 (solution 4) for existing designs that can't implement solution 2.
