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ArjunTechM's avatar
ArjunTechM
Icon for New Contributor rankNew Contributor
3 years ago

Error while adding the DDR Example design to top file : Error(21794): Quartus Prime Full Compilation

Am planning to use example design of DDR4 in one of my application project. But while integrating this DDR4 Example design as a component on Agilex FPGA: AGIB027R31B2E2VAA with their corresponding ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Arjun,


I have checked your design that you have attached.

I cannot reproduce the error that you have stated in previous comment but can see other error.


In this design, the alert pin is set to output port which is causing the error.

Change the alert pin port to input will resolve the error.

The change can be made in top level file at line 159.

Then you should be able to compile the design.


Please let me know if the issue still not resolve.


Regards,

Adzim