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saranya's avatar
saranya
Icon for New Contributor rankNew Contributor
4 years ago

Error while adding avalon signals in signal tap.

Beginner here. Trying to learn pcie. I have configured pcie(qsys) with 1 lane and gen2 speed.I have developed a test code,where 256 bytes of data were read and written from/to fpga through pcie. ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


thanks for your update. It seems weird as you are signaltap the Avalon signals but error trigger out related to the transceiver pin. Can you please help to create a simple test design with one PCIe instance + signaltap which could replicate the observation? I would like to further look into it. Thank you.


saranya's avatar
saranya
Icon for New Contributor rankNew Contributor
4 years ago

Hi,

As you mentioned, I had created a simple design with one PCIe instance only. I compiled the design without adding stp file,it got compiled.I didn't see any error.I face those errors only when I'm adding stp file and then compiling the design.

Is there any attribute in altera to mark the signals as debug signals in the design?

Thanks.