Dear Sir,
I need to modify a little for my question after got the user guide for the LVDS.
Because I made a mistake that choosing a non-DPA mode. I, however, got another
error message after setting it to a soft-CDR and compiled.
Error: Clock input port inclk[0] of PLL "altpll_sgmii:pll_sgmii_rx|altpll:altpll_component|altpll_sgmii_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block
Info: Input port INCLK[0] of node "altpll_sgmii:pll_sgmii_rx|altpll:altpll_component|altpll_sgmii_altpll:auto_generated|pll1" is driven by altlvds_rx_top:altlvds_rx_top|altlvds_rx:altlvds_rx_component|altlvds_rx_top_lvds_rx:auto_generated|wire_rx_divfwdclk[0]~_wirecell which is COMBOUT output port of Combinational cell type node altlvds_rx_top:altlvds_rx_top|altlvds_rx:altlvds_rx_component|altlvds_rx_top_lvds_rx:auto_generated|wire_rx_divfwdclk[0]~_wirecell
the inclock0 is driven by an output from a pll in 125Mhz. I don't know why it is not acceptable.
Regards,
Peter Chang
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Dear Sir,
I got one error message as below. It is for an IP from MegaWizard.
The IP is an LVDS with a SerDes. I don't know what the compensated input mean?
And, it seems that the LVDS has been set to a non-DPA mode. As far as I know,
the mode I need is soft-CDR for a SGMII interface. A little confused. There is
no option for the mode of soft-CDR.
Error: Input clock pin of fast PLL altlvds_rx_top:altlvds_rx_top|altlvds_rx:altlvds_rx_component|altlvds_rx_top_lvds_rx:auto_generated|pll, which drives at least one non-DPA-mode SERDES, must be driven by a compensated input
Regards,
Peter Chang
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