Honored Contributor
Honored ContributorOK, so it looks like you are on your way to unerstanding that choices made in the Simulink model will effect the "amount" of both logic and memory needs of the end HDL design.
The challenge now is to figure out what is sensitive to what. Think about how your control items may be effecting your logic structures. Think about the width of data paths, and how it will propogate through to either Flip flop generation or memory needs. If you have a 10 x 10 function, you will need 20 bits to store the result. Do you need to keep all 20 bits across the design (maybe resulting in 20 registers, times multiple ranks as it gets clocked through the design), or can you trim off some of the lower order bits? (At what cost to the quality of the end result?) (Simulation is good) It will take a little playing about and tugging here and there to get a feel for how much of what is created by this or that structure. Maybe use the RTL viewer to "see" what is getting generateed (as a way to pull back the layers of the code being generated). You are heading in the right direction.
