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What part are you targeting?
Can you look at the End of Synthesis rreport and see how many FPGA resources are being "authored" by the Matlab tool, and then Synthesized?
Try running Signal Compiler in Advanced mode (see the tab?), then just builed the project, then create the design files.
Then launch Quartus and open the project and just run Synthesis and see how many resources are being asked for?
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- I'm trying to compile the algorithms for the Device EP3C40F484C7 with 39,600 LE.
What do You mean with "create the design files"?
In Advanced Mode of Signal Compiler it is possibe to create the project, but not to run the Synthesis. The same error message (as in the Simple Mode by trying to compile) appears by trying this.
When I remove some parts from the project (which can be compiled separately), the project can be compiled. For the reduced project 20,423 LE are required.
Now, I will try to simplify some functions.
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