Honored Contributor
Honored ContributorWhat part are you targeting?
Can you look at the End of Synthesis rreport and see how many FPGA resources are being "authored" by the Matlab tool, and then Synthesized? Try running Signal Compiler in Advanced mode (see the tab?), then just build the project, then create the design files. Then launch Quartus and open the project and just run Synthesis and see how many resources are being asked for? Maybe you are blowing out of the top of the targeted part? ------ Or maybe you are targeting to large of a part? -------- You may need to look into doing some bit trimming along the way in your DSP design to reduce the needed resources, while still keeping the desired design intent. That is the beauty of modeling before compiling.
