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GIFT
New Contributor
5 years agoError 20445 in Tri Speed Ethernet IP for Stratix 10
Error(20445): The reference clock on PLL "ethernet_1g_top_inst|tx_side_ethernet_1g_inst|ethernet_multi_rate_ip_inst|eth_tse_0|i_lvdsio_0|core|arch_inst|pll_inst|internal_pll|stratix10_altera_iopll_i|...
Deshi_Intel
Regular Contributor
4 years agoHi,
There are 2 possibility that I can think of.
- You didn't assign the refclk pin to use "dedicated refclk" pin as indicated in the error message
- Did you assign the 2 TSE IP instance into same IO bank ?
- This will caused the error as stated in page 170, chapter 7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
- You need to split them into different IO bank
Thanks.
Regards,
dlim