Forum Discussion

BVola's avatar
BVola
Icon for New Contributor rankNew Contributor
6 years ago

Error 12006 when compiling clock buffer

I have a design instantiating two clock buffers (ALTIOBUF). The design synthesizes fine in Synplify Pro, but when I compile the netlist in Quartus Prime Lite, I get the error: Error (12006): Node ins...
BVola's avatar
BVola
Icon for New Contributor rankNew Contributor
6 years ago

I've included the .qip file. Not sure what you mean by "Instantiate ALTIOBUF..." Using the IP tool I created a module called "clk_buf"; THAT is instantiated at the top leve:

//clock buffers
	clk_buf CK_MAIN (
		.inclk  (clk_in),  
		.outclk (clk)  
	);
 
	clk_buf CK_SPI (
		.inclk  (spi_clk_in),  
		.outclk (spi_clk)  
	);