Hi frankbarone,
Here is the document for the read and write transfer in Avalon interface.
https://www.intel.com/content/www/us/en/docs/programmable/683091/20-1/transfers.html
The example design does not show the code because the traffic generator is controlling the memory.
Here a video that you can refer to: https://www.youtube.com/watch?v=sUXzuq8wmCg
This is the reference for traffic generator : https://www.intel.com/content/www/us/en/docs/programmable/683216/22-1-2-6-1/using-the-configurable-traffic-generator-tg2.html
Thanks.